october 2008 dsc-3834/10 1 ?2007 integrated device technology, inc. features 64k x 16 advanced high-speed cmos static ram equal access and cycle times ? commercial: 10/12/15/20ns ? industrial: 12/15/20ns one chip select plus one output enable pin bidirectional data inputs and outputs directly lvttl-compatible low power consumption via chip deselect upper and lower byte enable pins single 3.3v power supply available in 44-pin plastic soj, 44-pin tsop, and 48-ball plastic fbga packages description the idt71v016 is a 1,048,576-bit high-speed static ram organized as 64k x 16. it is fabricated using idt?s high-perfomance, high-reliability cmos technology. this state-of-the-art technology, combined with inno- vative circuit design techniques, provides a cost-effective solution for high- speed memory needs. the idt71v016 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. all bidirectional inputs and outputs of the idt71v016 are lvttl-compatible and operation is from a single 3.3v supply. fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. the idt71v016 is packaged in a jedec standard 44-pin plastic soj, a 44-pin tsop type ii, and a 48-ball plastic 7 x 7 mm fbga. functional block diagram output enable buffer address buffers chip enable buffer write enable buffer byte enable buffers oe a 0 ?a 15 row / column decoders cs we bhe ble 64k x 16 memory array sense amps and write drivers 16 low byte i/o buffer 8 8 8 8 i/o 8 i/o 15 i/o 7 i/o 0 3834 drw 01 high byte i/o buffer 3.3v cmos static ram 1 meg (64k x 16-bit) idt71v016sa/hsa
6.42 2 idt71v016sa, 3.3v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges 123456 a ble oe c b o bhe cs o c o o o o ss o c o e o c c o ss o o o o o c we o hc c pin configurations soj/tsop top view pin description truth table (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 i/o 7 nc a 12 a 13 a 14 a 15 we i/o 6 i/o 5 i/o 4 v ss v dd i/o 3 i/o 2 i/o 1 i/o 0 cs a 0 a 1 a 2 a 3 a 4 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a 6 a 7 oe bhe ble i/o 15 i/o 14 i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 nc a 5 nc so44-1 so44-2 3834 drw 02 note: 1. h = v ih , l = v il , x = don't care. cs oe we ble bhe o o o o h h h s llh l h o h lb l l h h l h o hb llh l l o o w l l l l ww l l l h h lbw l l h l h hbw l h h h h o l h h h h o bb
6.42 3 idt71v016sa, 3.3v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges symbol parameter 71v016sa10 71v016sa12 71v016sa15 71v016sa20 unit com'l only com'l ind com'l ind com'l ind i cc dynamic operating current cs cs cs absolute maximum ratings (1) recommended operating temperature and supply voltage dc electrical characteristics (v dd = min. to max., commercial and industrial temperature ranges) capacitance (t a = +25c, f = 1.0mhz, soj package) recommended dc operating conditions dc electrical characteristics (1,2) (v dd = min. to max., v lc = 0.2v, v hc = v dd ? 0.2v) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. for 71v016sa10 only. 2. for all speed grades except 71v016sa10. 3. v ih (max.) = v dd +2v for pulse width less than 5ns, once per cycle. 4. v il (min.) = ?2v for pulse width less than 5ns, once per cycle. note: 1. this parameter is guaranteed by device characterization, but not production tested. notes: 1. all values are maximum guaranteed values. 2. all inputs switch between 0.2v (low) and v dd ? 0.2v (high). 3. f max = 1/t rc (all address inputs are cycling at f max ); f = 0 means no address input lines are changing . 4. typical values are based on characterization data for h step only measured at 3.3v, 25c and with equal read and write cycles . symbol rating value unit v dd supply voltage relative to v ss ?0.5 to +4.6 v v in , v out terminal voltage relative to v ss ?0.5 to v dd +0.5 v t bias temperature under bias ?55 to +125 o c t stg storage temperature ?55 to +125 o c p t power dissipation 1.25 w i out dc output current 50 ma 3834 tbl 03 grade temperature v ss v dd commercial 0c to +70c 0v see below industrial -40c to +85c 0v see below 3834 tbl 04 symbol parameter min. typ. max. unit v dd (1) supply voltage 3.15 3.3 3.6 v v dd (2) supply voltage 3.0 3.3 3.6 v vss ground 0 0 0 v v ih input high voltage 2.0 ___ _ v dd +0.3 (3) v v il input low voltage ?0.3 (4 ) ___ _ 0.8 v 3834 tbl 05 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 6 pf c i/ o i/o capacitance v out = 3dv 7 pf 3834 tbl 06 symbol parameter test condition idt71v016sa unit min. max. |i li | input leakage current v dd = max., v in = v ss to v dd ___ 5a |i lo | output leakage current v dd = max., cs h o ss ol o l ol oh o h oh
6.42 4 idt71v016sa, 3.3v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges ac test conditions ac test loads figure 3. output capacitive derating figure 1. ac test load figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow, and t whz ) *including jig and scope capacitance. +1.5v 50 ? ? ? ? ? ? ? ? ? ? ?
6.42 5 idt71v016sa, 3.3v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges 71v016sa10 (2 ) 71v016sa12 71v016sa15 71v016sa20 symbol parameter min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 10 ____ 12 ____ 15 ____ 20 ____ ns t aa address access time ____ 10 ____ 12 ____ 15 ____ 20 ns t acs chip select access time ____ 10 ____ 12 ____ 15 ____ 20 ns t cl z (1) chip select low to output in low-z 4 ____ 4 ____ 5 ____ 5 ____ ns t chz (1 ) chip s elect high to output in high-z ____ 5 ____ 6 ____ 6 ____ 8ns t oe outp ut enable low to output valid ____ 5 ____ 6 ____ 7 ____ 8ns t ol z (1 ) output enable low to output in low-z 0 ____ 0 ____ 0 ____ 0 ____ ns t ohz (1) output e nable high to output in high-z ____ 5 ____ 6 ____ 6 ____ 8ns t oh output hold from address change 4 ? 4 ? 4 ? 4 ? ns t be by te enable low to output valid ? 5 ? 6 ? 7 ____ 8ns t blz (1) byte enable low to output in low-z 0 ____ 0 ____ 0 ____ 0 ____ ns t bhz (1 ) byte e nable high to output in high-z ____ 5 ____ 6 ____ 6 ____ 8ns writ e cycle t wc write cycle time 10 ____ 12 ____ 15 ____ 20 ____ ns t aw address valid to end of write 7 ____ 8 ____ 10 ____ 12 ____ ns t cw chip select lo w to end of write 7 ____ 8 ____ 10 ____ 12 ____ ns t bw byte enable lo w to end of write 7 ____ 8 ____ 10 ____ 12 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wr address hold from end of write 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 7 ____ 8 ____ 10 ____ 12 ____ ns t dw data valid to end of write 5 ____ 6 ____ 7 ____ 9 ____ ns t dh data hold time 0 ____ 0 ____ 0 ____ 0 ____ ns t ow (1 ) write enable high to output in low-z 3 ____ 3 ____ 3 ____ 3 ____ ns t whz (1 ) write enable low to output in high-z ____ 5 ____ 6 ____ 6 ____ 8ns 3834 tb l 10 timing waveform of read cycle no. 1 (1,2,3) notes: 1. we hh c cs low oe bhe ble low ac electrical characteristics (v dd = min. to max., commercial and industrial temperature ranges) data out address 3834 drw 06 t rc t aa t oh t oh data out valid previous data out valid notes: 1. this parameter is guaranteed with the ac load (figure 2) by device characterization, but is not production tested. 2. 0
6.42 6 idt71v016sa, 3.3v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges timing waveform of read cycle no. 2 (1) notes: 1. a write occurs during the overlap of a low cs low bhe ble low we oe hh we oe low w wh w o w oe hh we w o cs low bhe ble low we low timing waveform of write cycle no. 1 ( we controlled timing) (1,2,4) notes: 1. we hh c cs bhe ble low ess oe cs o l c oe ol ch oh o bhe ble cs bl cl be oh bh ess cs l wc s wh cw ch ow w we w o w h eos l l bhe ble bw w bh
6.42 7 idt71v016sa, 3.3v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges timing waveform of write cycle no. 2 ( cs controlled timing) (1,4) notes: 1. a write occurs during the overlap of a low cs low bhe ble low we oe hh we oe low w wh w o w oe hh we w o cs low bhe ble low we low timing waveform of write cycle no. 3 ( bhe , ble controlled timing) (1,4) address cs data in 3834 drw 09 data in valid t wc t as (2) t cw t wr we t aw data out t dw t dh bhe , ble t bw t wp address cs data in 3834 drw 10 data in valid t wc t as (2) t cw t wr we t aw data out t dw t dh bhe, ble t bw t wp
6.42 8 idt71v016sa, 3.3v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges ordering information sa power xx speed xxx package x process/ temperature range blank i commercial (0c to +70c) industrial (-40c to +85c) y ph bf 400-mil soj (so44-1) 400-mil tsop type ii (so44-2) 7.0 x 7.0 mm fbga (bf48-1) 10** 12 15 20 71v016 device type speed in nanoseconds 3834 drw 11 ** commercial temperature range only. x tape & reel 8 x g restricted hazardous substance device h current generation die step optional h first generation or current stepping blank
the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 9 idt71v016sa, 3.3v cmos static ram 1 meg (64k x 16-bit) commercial an d industrial temperature ranges corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or ipchelp@idt.com san jose, ca 95138 408-284-8200 800-345-7015 fax: 408-284-2775 www.idt.com 1/7/00 updated to new format pp. 1, 3, 5, 8 added industrial temperature range offerings pg. 2 numbered i/os and address pins on fbga top view pg. 6 revised footnotes on write cycle no. 1 diagram pg. 7 revised footnotes on write cycle no. 2 and no. 3 diagrams pg. 9 added datasheet document history 08/30/00 pg. 3 tighten i cc and i sb . pg. 5 tighten t clz , t chz, t ohz , t bhz and t whz 08/22/01 pg. 8 removed footnote "available in 15ns and 20ns only" 06/20/02 pg. 8 added tape and reel field to ordering information 01/30/04 pg. 8 added "restricted hazardous substance device" to ordering information. 09/27/06 pg. 8 corrected ordering information, changed position of i and g. 02/14/07 pg.8 added h step generation to data sheet ordering information. 06/26/07 pg.3 changed typical parameters for icc, dc electrical characteristics table. 10/13/08 pg.8 removed "idt" from orderable part number
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